module fdiv1_8(clk,rst,N,clk_out);
input clk,rst;
input [3:0] N;
output clk_out;
wire clk_out;
reg COUT1,COUT2,COUT3;
reg[3:0] m,n,k;
wire flag;

assign flag=N[0]&1'b1;

//偶数分频
always @(posedge clk)
begin 
	if(!rst)
		begin k<=0; COUT1<=0;end
	else	
		if(!flag) begin
			if(k==N-1)begin k<=0; COUT1<=~COUT1;end
			if(k==N/2-1)begin k<=0;COUT1<=~COUT1;end
			else k<=k+3'b1;
		end
	end
 
 //奇数分频1
 always @(posedge clk)
 begin
	if(!rst)
		begin m<=0; COUT2<=0;end
	else 
		if(flag) begin
			if(m==N-1) m<=0;
			else m<=m+3'b1;
			if(m==(N+1)/2-1) COUT2<=~COUT2;
			else if(m==N-2) COUT2<=~COUT2;
	end
 end
 
 //奇数分频2
 always @(negedge clk)
 begin
	if(!rst)
		begin n<=0; COUT3<=0;end
	else 
		if(flag) begin
			if(n==N-1) n<=0;
			else n<=n+3'b1;
			if(n==(N+1)/2-1) COUT3<=~COUT3;
			else if(n==N-2) COUT3<=~COUT3;
	end
 end
assign clk_out=(flag)?(COUT2|COUT3):COUT1;
/*
always@(posedge clk)
begin
	if(!flag)
		clk_out<=COUT1;
	else
		clk_out<=COUT2|COUT3;
end
*/
endmodule
